Udemy - VLSI/FPGA Design P4: STA && DC Synthesis

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Free Download Udemy - VLSI/FPGA Design P4: STA && DC Synthesis
Last updated 4/2025
MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz, 2 Ch
Language: English | Duration: 7h 56m | Size: 3.65 GB
Static Timing Analysis and DC Synthesis

What you'll learn
Principle of STA
Basics of stander cell library
Characters of clock in STA
Setup/hold timing analysis for same clock
Common used timing constraints
Timing analysis for same clock domain (synchronous path)
Timing analysis for different clock domain (asynchronous path)
Synthesis example using Design Compiler (including whole TCL script)
Requirements
Basic knowledge of digital fundamental
Description
Who this course is for
Senior undergraduate students of EE or higher
IC design/verification engineers with 0~2 year experience
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