Source Synchronous Networks On Chip Circuit And Architectural Interconnect Modeling

[Farid]

English | 156 pages | Springer; 2014th edition (November 19, 2013) | 1461494044 | PDF | 6 Mb

Source-Synchronous Networks-On-Chip (Ayan Mandal) (2013)
Catergory: Computer Technology, Technology, Engineering, Nonfiction
Publisher: Springer New York

This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.

🌞 Contents of Download:
📌 1461494044.pdf (Ayan Mandal) (2013) (6.4 MB)

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⭐️ Source Synchronous Networks On Chip Circuit And Architectural Interconnect Modeling ✅ (6.4 MB)
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