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+--- Thread: Testing of Interposer-Based 2.5D Integrated Circuits (/Thread-Testing-of-Interposer-Based-2-5D-Integrated-Circuits)
Testing of Interposer-Based 2.5D Integrated Circuits - Farid - 10-03-2023
![[Image: NZSPiW.u4rce4w4dj5g.jpg]](https://i.im.ge/2023/10/03/NZSPiW.u4rce4w4dj5g.jpg)
439840_Print.indd | 192 |
This book provides readers with an insightful guide to the design, testing and optimization of 2.5D integrated circuits. The authors describe a set of design-for-test methods to address various challenges posed by the new generation of 2.5D ICs, including pre-bond testing of the silicon interposer, at-speed interconnect testing, built-in self-test architecture, extest scheduling, and a programmable method for low-power scan shift in SoC dies. This book covers many testing techniques that have already been used in mainstream semiconductor companies. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 2.5D ICs a reality and commercially viable.
Contents of Download:
Testing of Interposer-Based 2.5D Integrated Circuits.pdf (12.52 MB)
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