Quote:Whats New in Version 11.0 (Build 1000) 13/Jun/2024
New Features
       Added new configuration file parameter CHECKMEMSPEED for verifying whether the configured memory speed is consistent with one of the SPD profiles or an arbitrary minimum speed specified by the user. If this check fails, an error message is displayed and the memory test will not start. This is useful for confirming that the memory tests are carried out at the maximum speed supported by the RAM.
       Added new configuration file parameter TCPREQUESTLOCATION for specifying the URL request path (and cloud API key) for PassMark Management Console integration
       Added new configuration file parameter TCPGATEWAYIP for setting the default gateway route IP address to allow for connections outside the local network for PassMark Management Console integration
       Added new configuration file parameter SPDREPORTEXTSN for specifying whether to use the module?s extended, 18-digit serial number or standard 8-digit JEDEC serial number in reports. The extended serial number encodes additional manufacture information (including the manufacture ID, date and location) and is more likely to match the serial number printed on the label of the RAM module.
       Added new configuration file parameter DISABLESPD for disabling SPD collection. This is a workaround to prevent throttling of memory speeds, which results in increased test times. This occurs when reading SPD data interferes with the chipset?s Closed-Loop Thermal Throttling (CLTT) mechanism. CLTT is used on a small number of server motherboards to reduce the speed of RAM access when temperatures are too high. But in this case the throttling was seen to be incorrectly activated, due to what we suspect is a BIOS bug.
       Added new configuration file parameter TSODPOLL to enable/disable polling of DIMM temperature sensors (if available). Polling is on by default.
       Preliminary address module decoding support for Intel Meteor Lake/Arrow Lake chipsets. This can help pinpoint the physical location of a memory error.
       Support for collecting memory timings periodically during the test session. When the test completes, the lowest/highest memory speeds are reported. Some motherboard vary timings in a dymanic fashion.
       Added support for reporting AMD EXPO profiles in DDR5 SPD. EXPO allows for running the RAM at faster than normal speeds without manual overclocking. As always, MemTest86 never changes the BIOS settings. This is just a change to report what profiles are available.
   Fixes/Enhancements
       Added TLS (encrypted data) support for PassMark Management Console integration. This is only used when sending test results to the central database for record keeping.
       Added DNS support for PassMark Management Console integration
       Added support for new DDR5 form factors "CDIMM", "CSODIMM" and "CAMM2" for CHIPMAP configuration file parameter. This is to support the new clocked (CUDIMM/CSODIMM) and compact (CAMM2/LPCAMM2) DDR5 form factors supported by newer chipsets (eg. Intel Arrow Lake).
       Increased maximum string length of chip labels to 6 for CHIPMAP configuration file parameter. This is to support longer names used in CUDIMM, CSODIMM and CAMM2 component labels such as ?DAR0B0?.
       Fixed bug in address module decoding on Intel Comet Lake chipsets
       Fixed incorrect channel mode detection for the following chipsets:
           AMD Ryzen
           Intel Coffee Lake
           Intel Comet Lake
           Intel Ice Lake
           Intel Rocket Lake
           Intel Tiger Lake
           Intel Elkhart Lake
       Fixed incorrect memory timings detection for the following chipsets:
           AMD Ryzen
           Intel Meteor Lake
           Intel Arrow Lake
           Intel Ice Lake-SP
           Intel Emerald Rapids-SP chipsets
       Fixed incorrect clock speed detection for the following chipsets:
           Intel Rocket Lake
           Intel Ice Lake
           Intel Tiger Lake
           Intel Alder Lake
           Intel Meteor Lake
           Intel Arrow Lake
           Intel Elkhart Lake
           Intel Ice Lake-SP
           Intel Emerald Rapids-SP
       Preliminary support for obtaining memory settings for the following AMD chipsets:
           AMD K8
           AMD K10
           AMD Bulldozer
           AMD Piledriver
           AMD Steamroller
           AMD Excavator
           AMD Jaguar
           AMD Puma
       Preliminary support for multithreading on ARM64, which was previously unavailable due to UEFI BIOS limitations
       Fixed issue with reading DDR5 SPD when the SPD page has not been reset to zero
       Fixed ECC injection option not available on AMD Ryzen Zen 3 chipsets. Note that in general ECC injection is not a feature that is normally accessible by end-users and typically requires a custom BIOS.
       Fixed In-band ECC (IBECC) capability detection on the following chipsets:
           Intel Tiger Lake
           Intel Alder Lake
           Intel Meteor Lake
           Intel Arrow Lake
           Intel Elkhart Lake
       Fixed ECC capability detection on Intel Ice Lake-SP and Emerald Rapids-SP chipsets
       Fixed reporting of invalid DIMM temperatures by adding checks for valid Temperature Sensor on DIMM (TSOD) raw data
       Added support for retrieving Intel Meteor Lake and Arrow Lake CPU information
       Updated Chinese and Japanese localization strings (courtesy of Nagisa)
       Updated blacklist to work around specific mainboards/BIOSes with known UEFI multithreading and other issues