Udemy - RTL Fundamentals in System Verilog - Printable Version +- Softwarez.Info - Software's World! (https://softwarez.info) +-- Forum: Library Zone (https://softwarez.info/Forum-Library-Zone) +--- Forum: Video Tutorials (https://softwarez.info/Forum-Video-Tutorials) +--- Thread: Udemy - RTL Fundamentals in System Verilog (/Thread-Udemy-RTL-Fundamentals-in-System-Verilog) |
Udemy - RTL Fundamentals in System Verilog - AD-TEAM - 09-20-2024 932.95 MB | 00:05:04 | mp4 | 1280X720 | 16:9 Genre:eLearning |Language:English
Files Included :
1 How to use this course (5.39 MB) 2 Intro - Part 1 (7.8 MB) 3 Intro - Part 2 (9.92 MB) 1 Gate Simulation Ripple Adder (46.44 MB) 1 Clean up (11.49 MB) 2 (Optional) Simulate in EdaPlayground com (11.06 MB) 1 Intro (11.86 MB) 2 Design by Simulation Trap - Part 1 (9.09 MB) 3 Design by Simulation Trap - Part 2 (15.32 MB) 4 RTL Naming Convention - Part 1 (10.25 MB) 5 RTL Naming Convention - Part 2 (13.57 MB) 6 RTL Naming Convention - Part 3 (11.29 MB) 7 RTL Naming Convention - Part 4 (11.93 MB) 1 GCD Algorithm to RTL (9.64 MB) 2 Hardware InputOutput (3.41 MB) 3 InputOutput Waveforms (8.98 MB) 4 Waveform-Look-Left (12.65 MB) 1 GCD RTL - Part 1 (13.31 MB) 2 Default Assignments (15.03 MB) 3 GCD RTL - Part 2 (29.58 MB) 1 GCD Testbench - Part 1 (23.2 MB) 2 GCD Testbench - Part 2 (20.05 MB) 3 GCD Testbench - Part 3 (13.1 MB) 1 GCD Simulation Part 1 (11.78 MB) 2 GCD Simulation Part 2 (21.13 MB) 1 GCD Synthesis Part 1 (26.72 MB) 2 GCD Synthesis Part 2 (20.44 MB) 1 Alternative RTL Implementation (15.09 MB) 2 Simulate & Synthesize (25.03 MB) 3 Not Recommended Why (12.67 MB) 1 Wrap Up (8.94 MB) 12 EDA Playground Hints (Optional) (26.34 MB) 2 Docker Windows Install (Optional) (14.03 MB) 4 Download Docker Image (7.13 MB) 6 Run Docker with GUI (Windows) (6.65 MB) 9 Test Install (7.68 MB) 1 Latches vs Flip Flops (11.18 MB) 2 Docker Intro (12.35 MB) 1 The Compute Machine (20.15 MB) 2 RTL Abstraction Details (15.59 MB) 1 Intro - Part 1 (12.52 MB) 2 Intro - Part 2 (7.44 MB) 3 Modules & Signals (12.24 MB) 4 Procedural Block - Part 1 (18.81 MB) 5 Procedural Block - Part 2 (10.06 MB) 6 Continuous Assignments (20.27 MB) 7 Event (@) Expressions (11.91 MB) 8 Rules - Part 1 (17.01 MB) 9 Rules - Part 2 (10.11 MB) 1 Binary Adder Theory (14.98 MB) 2 Ripple Adder Module Definition (16.26 MB) 3 Half Adder Function (5.42 MB) 4 Full Adder Function (14.54 MB) 5 Ripple Adder (34.66 MB) 1 Testbench Part 1 (19.09 MB) 2 Testbench Part 2 (21.55 MB) 1 Docker Command (8.96 MB) 2 RTL Simulation Part 1 (19.33 MB) 3 RTL Simulation Part 2 (23.22 MB) 1 Synthesis (35.06 MB) 2 Gate Netlist (12.23 MB)
Screenshot
|