Udemy - Design Verification With Systemverilog/UVM

Udemy - Design Verification With Systemverilog/UVM - Printable Version

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Udemy - Design Verification With Systemverilog/UVM - OneDDL - 03-12-2025

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Free Download Udemy - Design Verification With Systemverilog/UVM
Published: 3/2025
MP4 | Video: h264, 1920x1080 | Audio: AAC, 44.1 KHz
Language: English | Size: 12.89 GB | Duration: 21h 19m
Unveiling UVM in SystemVerilog Language: From Building UVM Agents to Functional Coverage and Debugging Techniques

What you'll learn
Module level verification using SystemVerilog and UVM library.
Build agents in SystemVerilog/UVM to drive and monitor communication interfaces.
Build the model of the registers using UVM and connect it to the APB interface in order to let UVM perform its automatic checks on the register accesses.
Build the functional model of a Device Under Test (DUT) and use it to predict the correct response expected from the DUT.
Build a scoreboard to verify automatically all the expected outputs of a DUT.
Build the coverage model and all the logic necessary to collect that coverage.
Build random tests to verify all the features of a DUT.
Learn how to deal with synchronization issues in the model.
Requirements
You need to have a basic understanding of digital integrated circuits and how they are modeled in a HDL language like Verilog.
There is no hard requirement for your to know SystemVerilog but prior OOP and Verilog knowledge is required.
Description
Master UVM Library & Create a Verification Environment: Comprehensive Course OverviewIn this course, you'll delve into two crucial areas:UVM Library: Uncover all its features, secrets, and how they can be applied effectively in verification environments.Verification Environment Creation: Learn the step-by-step process of building a robust verification environment from the ground up using UVM.Course Objectives:Throughout this course, we'll guide you through the development of a verification environment, meticulously designed using the UVM library. Each tutorial will introduce new functionalities, demonstrating the UVM features necessary for each phase of our comprehensive project.We'll leverage the EDA Playground platform to develop our verification environment. By the end of the course, our final project will encompass over 5000 lines of code, providing a substantial showcase of your acquired skills and knowledge.By the end of this course, you will master:Building UVM agents and understanding their rolesModeling design registers using the UVM librarySetting up a Device Under Test (DUT) within a verification environmentVerifying the outputs of a DUT to ensure accuracy and functionalityImplementing functional coverage in SystemVerilog to achieve thorough verificationWriting and executing random tests to cover a wide range of scenariosEmploying advanced debugging techniques to identify and resolve issuesExploring and utilizing hidden features of the UVM library to enhance your projectsThe skills you gain from this course will not only prepare you for entry or junior-level verification engineer job interviews but will also ensure you are productive and effective from day one in your new role.
Overview
Section 1: Introduction
Lecture 1 Introduction
Lecture 2 What is Design Verification
Lecture 3 Device Under Test (DUT)
Lecture 4 Environment Architecture
Lecture 5 Environment Coding Kick Off - Lecture
Lecture 6 Environment Coding Kick off - Practice - Info
Lecture 7 Environment Coding Kick Off - Practice
Section 2: The Basics in Building an UVM Agent
Lecture 8 APB Agent Infrastructure - Lecture
Lecture 9 APB Agent Infrastructure - Practice - Info
Lecture 10 APB Agent Infrastructure - Practice
Lecture 11 APB Driving Item - Lecture
Lecture 12 APB Driving Item - Practice - Info
Lecture 13 APB Driving Item - Practice
Lecture 14 APB Sequence Mechanism - Lecture
Lecture 15 APB Sequence Mechanism - Practice - Info
Lecture 16 APB Sequence Mechanism - Practice
Lecture 17 APB Driver - Lecture
Lecture 18 APB Driver - Practice - Info
Lecture 19 APB Driver - Practice
Lecture 20 APB Monitor - Lecture
Lecture 21 APB Monitor - Practice - Info
Lecture 22 APB Monitor - Practice
Lecture 23 APB Protocol Checks - Lecture
Lecture 24 APB Protocol Checks - Practice - Info
Lecture 25 APB Protocol Checks - Practice
Lecture 26 APB Coverage - Lecture
Lecture 27 APB Coverage - Practice - Info
Lecture 28 APB Coverage - Practice
Lecture 29 APB Reset Handling - Lecture
Lecture 30 APB Reset Handling - Practice - Info
Lecture 31 APB Reset Handling - Practice
Lecture 32 APB Agent - Conclusions
Section 3: Building Reusable UVM Agents
Lecture 33 Memory Data (MD) Protocol
Lecture 34 MD Agent Architecture
Lecture 35 MD Agent Infrastructure - Lecture
Lecture 36 MD Agent Infrastructure- Practice - Info
Lecture 37 MD Agent Infrastructure - Practice
Lecture 38 MD Master Driving Logic - Lecture
Lecture 39 MD Master Driving Logic - Practice - Info
Lecture 40 MD Master Driving Logic - Practice
Lecture 41 MD Monitor - Lecture
Lecture 42 MD Monitor - Practice - Info
Lecture 43 MD Monitor - Practice
Lecture 44 MD Slave Driving Logic - Lecture
Lecture 45 MD Slave Driving Logic - Practice - Info
Lecture 46 MD Slave Driving Logic - Practice
Lecture 47 MD Protocol Checks - Lecture
Lecture 48 MD Protocol Checks - Practice - Info
Lecture 49 MD Protocol Checks - Practice
Lecture 50 MD Coverage - Lecture
Lecture 51 MD Coverage - Practice - Info
Lecture 52 MD Coverage - Practice
Lecture 53 MD Agent - Conclusions
Section 4: Advanced Technique For Building UVM Agents
Lecture 54 Advanced Technique for Building UVM Agents - Introduction
Lecture 55 UVM Extension Agent Configuration - Lecture
Lecture 56 UVM Extension Agent Configuration - Practice - Info
Lecture 57 UVM Extension Agent Configuration - Practice
Lecture 58 UVM Extension Monitor - Lecture
Lecture 59 UVM Extension Monitor - Practice - Info
Lecture 60 UVM Extension Monitor - Practice
Lecture 61 UVM Extension Coverage - Lecture
Lecture 62 UVM Extension Coverage - Practice - Info
Lecture 63 UVM Extension Coverage - Practice
Lecture 64 UVM Extension Sequencer - Lecture
Lecture 65 UVM Extension Sequencer - Practice - Info
Lecture 66 UVM Extension Sequencer - Practice
Lecture 67 UVM Extension Driver - Lecture
Lecture 68 UVM Extension Driver - Practice - Info
Lecture 69 UVM Extension Driver - Practice
Lecture 70 UVM Extension Agent - Lecture
Lecture 71 UVM Extension Agent - Practice - Info
Lecture 72 UVM Extension Agent - Practice
Lecture 73 UVM Extension Package - Conclusions
Section 5: UVM Register Model
Lecture 74 UVM Register Model - Introduction
Lecture 75 UVM Register Field - Lecture
Lecture 76 UVM Register - Lecture
Lecture 77 UVM Register Field and UVM Register - Practice - Info
Lecture 78 UVM Register Field and UVM Register - Practice
Lecture 79 UVM Register Block - Lecture
Lecture 80 UVM Register Block - Practice - Info
Lecture 81 UVM Register Block - Practice
Lecture 82 Integration with Bus Monitor - Lecture
Lecture 83 Integration with Bus Monitor - Practice - Info
Lecture 84 Integration with Bus Monitor - Practice
Lecture 85 Custom Register Predictor - Lecture
Lecture 86 Custom Register Predictor - Practice - Info
Lecture 87 Custom Register Predictor - Practice
Lecture 88 Integration with Bus Sequencer - Lecture
Lecture 89 Integration with Bus Sequencer - Practice - Info
Lecture 90 Integration with Bus Sequencer - Practice
Lecture 91 Register Field Callback - Lecture
Lecture 92 Register Field Callback - Practice - Info
Lecture 93 Register Field Callback - Practice
Lecture 94 UVM Register Model - Conclusions
Section 6: Modeling and Checking
Lecture 95 Modeling and Checking - Introduction
Lecture 96 Model Architecture
Lecture 97 Model Interface - Lecture
Lecture 98 Model Interface - Practice - Info
Lecture 99 Model Interface - Practice
Lecture 100 Model Illegal RX Accesses - Lecture
Lecture 101 Model Illegal RX Accesses - Practice - Info
Lecture 102 Model Illegal RX Accesses - Practice
Lecture 103 Model Legal RX Accesses - Lecture
Lecture 104 Model Legal RX Accesses - Practice - Info
Lecture 105 Model Legal RX Accesses - Practice
Lecture 106 Model Intermediate Buffer - Lecture
Lecture 107 Model Intermediate Buffer - Practice - Info
Lecture 108 Model Intermediate Buffer - Practice
Lecture 109 Model Align Logic - Lecture
Lecture 110 Model Align Logic - Practice - Info
Lecture 111 Model Align Logic - Practice
Lecture 112 Model TX Controller - Lecture
Lecture 113 Model TX Controller - Practice - Info
Lecture 114 Model TX Controller - Practice
Lecture 115 Scoreboard Architecture
Lecture 116 Scoreboard Interface - Lecture
Lecture 117 Scoreboard Interface - Practice - Info
Lecture 118 Scoreboard Interface - Practice
Lecture 119 Scoreboard Check: RX Response - Lecture
Lecture 120 Scoreboard Check: RX Response - Practice - Info
Lecture 121 Scoreboard Check: RX Response - Practice
Lecture 122 Scoreboard Check: TX Item - Lecture
Lecture 123 Scoreboard Check: TX Item - Practice - Info
Lecture 124 Scoreboard Check: TX Item - Practice
Lecture 125 Scoreboard Check: IRQ - Lecture
Lecture 126 Scoreboard Check: IRQ - Practice - Info
Lecture 127 Scoreboard Check: IRQ - Practice
Lecture 128 Model Synchronization: FIFO Flags - Lecture
Lecture 129 Model Synchronization: FIFO Flags - Practice - Info
Lecture 130 Model Synchronization: FIFO Flags - Practice
Lecture 131 Model Synchronization: Push & Pop - Lecture
Lecture 132 Model Synchronization: Push & Pop - Practice - Info
Lecture 133 Model Synchronization: Push & Pop - Practice
Lecture 134 Model Synchronization: Overlapping IRQs - Lecture
Lecture 135 Model Synchronization: Overlapping IRQs - Practice - Info
Lecture 136 Model Synchronization: Overlapping IRQs - Practice
Lecture 137 DUT Functional Coverage - Lecture
Lecture 138 DUT Functional Coverage - Practice - Info
Lecture 139 DUT Functional Coverage - Practice
Lecture 140 Virtual Sequencer - Lecture
Lecture 141 Virtual Sequencer - Practice - Info
Lecture 142 Virtual Sequencer - Practice
Lecture 143 Modeling and Checking - Conclusions
Section 7: Debug and Tests
Lecture 144 Debug and Tests - Introduction
Lecture 145 UVM Messages - Lecture
Lecture 146 UVM Messages - Practice - Info
Lecture 147 UVM Messages - Practice
Lecture 148 UVM Transactions
Lecture 149 Debugging Technique: Track the Source
Lecture 150 Tests Organization
Lecture 151 Tests: Register Access - Lecture
Lecture 152 Tests: Register Access - Practice - Info
Lecture 153 Tests: Register Access - Practice
Lecture 154 Tests: Random Traffic - Lecture
Lecture 155 Tests: Random Traffic - Practice - Info
Lecture 156 Tests: Random Traffic - Practice
Lecture 157 Tests: Illegal RX Traffic - Lecture
Lecture 158 Tests: Illegal RX Traffic - Practice - Info
Lecture 159 Tests: Illegal RX Traffic - Practice
Lecture 160 Debug and Tests - Conclusions
Section 8: Wrapping Up
Lecture 161 Stages of a Verification Project
Lecture 162 Outro
Students and engineers who want to learn how to do module level verification using SystemVerilog language and UVM library.

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