Siemens PADS Standard Plus (VX 2.15)

[Farid]

Publisher: Siemens Digital Industries Software
Year of manufacture: 2024
Interface language: Russian, Multilingual
Version: VX 2.15
Name: Siemens PADS Standard Plus
Size: 6.66 GB
Tablet: Present

Description:
New Features Introduced in PADS VX.2.15
This release is primarily aimed at adding new features and fixing customer reported defects called Service Requests (SRs). The PADS VX.2.15 release introduces the following new products, features, and enhancements.

HyperLynx AMS
HyperLynx AMS (formerly PADS AMS) includes the following updates in the PADS VX.2.15 release.
PADS AMS renamed to HyperLynx AMS
The PADS AMS simulator has been renamed to HyperLynx AMS. This name change is made only to better align the simulator with the family of analysis and verification tools in the Electronic Board Systems division of Siemens EDA. You will now see "HyperLynx AMS" rather than "PADS AMS" in menus and dialog boxes when you install and use the tool. Reorganized list of options in the option selection dialog
When setting up a sweep-based analysis, a parameter selection dialog box helps you select parameters to change during the simulation. Network names in the options dialog are now organized hierarchically by component name.
Removed assigned contacts from the contact matching tool list
When selecting a simulation model for a symbol, you must ensure that the symbol's pins are properly connected to the model's ports. The Contact Mapping tool in the Model and Symbol Wizard and Edit Model Properties dialog boxes helps with this mapping. In VX.2.15, the Contact Mapping Tool has been updated so that once you select a symbol contact to match, it no longer appears in the list of possible contacts to assign.

HyperLynx® DRC
The sections below provide information about the changes in this release of HyperLynx DRC products.
Export CCE file with cropping function for HL SI
New CCE export support improves rule performance by truncating constructs
Object-based region clipping - clips the structure at a fixed distance from specific objects of interest (e.g. nets, pins, etc.)
Coordinate-based area cropping-cuts a structure by specifying coordinates
Increased accuracy
One nanometer resolution
Improvement of geometric resolution from 10 nm to 1 nm
Increased accuracy during analysis operations
Negotiate expected resolution with Xpedition and other EDA streams
New Trace Modeler - improved calculations to more accurately match the SI product
Improved precision of assembly component contours in Allegro Translation

HyperLynx SI/PI/Thermal
This release contains the following improvements, as well as numerous defect fixes and security improvements.
General improvements
Simplified configuration of IBIS-AMI models for DDR5/LPDDR5(X) simulation
IBIS-AMI simulation of DDR5/LPDDR5(X) command/address bus simulation
Simplified setup for DDR5/LPDDR5(X) simulation when using IBIS only models

DDRx
The DDRx Batch Wizard GUI has been improved to make the user experience easier. Prior to VX.2.15, the configuration of IBIS-AMI models was spread across multiple pages and required careful controller/DRAM selection. Now in VX.2.15, the configuration of IBIS-AMI models for an operation can be viewed and configured on one page of the wizard.
The DDRx Batch Wizard now supports IBIS-AMI unbuffered command/address bus modeling for DDR5/LPDDR5(X). Prior to VX.2.15, this feature was only available for registered DIMMs (RDIMMs). Now in VX.2.15, HyperLynx can incorporate effects such as Tx controller alignment and IBIS-AMI jitter/noise parameters into the command/address bus simulation.
DDR5
For DDR5/LPDDR5(X) simulations, the DDRx Batch Wizard now automatically replaces AMI executables when it detects an IBIS-only buffer model. Prior to VX.2.15, this required manual editing of the IBIS model text file. By performing automatic replacement, the user saves time and hassle and can focus on moving toward simulation results.

Ability to view modern 3D boards
Standard integrated SI/PI part
Full 3D board view or partial area view
Select and highlight networks synchronously between 2D and 3D views
Improved highlighting and transparency controls for objects of interest

SERDES compliance
New Compliance Wizard protocol support for
OIF CEI-224G-MR-PAM4
PCIe Gen 6 Add-in-Card
System board channels
Support for Rx FFE COM 4.1 algorithms
HTML report adds Worst/Best Case Rx FFE tap weight table
Improved 100G Ethernet and OIF COM algorithms
Updated protocols, including corrections
100G Ethernet и OIF
PCIe Gen 4.5 and 6
MIPI D-PHY modes 0-4
10GBASE-KR and 40GBASE-KR4

System Requirements:
- Supported processors and systems are those manufactured since 2008 and comply
following requirements.
- The minimum requirement is a dual-core (or dual-processor) system. To improve overall system performance, a quad-core processor is recommended. Processor with hyperthreading support
should be considered a single processor, not a dual processor.
- Intel Celeron processors are not recommended.
- For best results, maximize CPU speed and L1/L2/L3 CPU cache.
- Cost is usually the best indicator of performance, with additional investment in processor capabilities
return better system performance.
Processor: Minimum dual-core Intel or AMD processor. See Processor Note for Intel/AMD processors above.
Memory: 8 GB recommended
Swap space: 2 times the amount of RAM

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⭐️ Siemens PADS Standard Plus (VX 2.15) ✅ (6.66 GB)
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